In many cases, an IC chip is installed in a package including a plurality of terminals, in accordance with the wire bonding method. Generally, in the wire bonding method used for the installation of the IC chip in the package, an appropriate size of the package and respective positions (layout) of the terminals are determined in accordance with (i) the size of the IC chip, (ii) the number of terminals required for the installation of the IC chip, and (iii) simplicity in a wire layout.
The following explains (i) an example of a conventional method for designing, based on an IC package including a plurality of circuit blocks, an IC package using only a part of functions of the circuit blocks; and (ii) an example of a conventional method for manufacturing such an IC package. The explanation will be made with reference to FIG. 5(a) through FIG. 5(c), and FIG. 6(a) through FIG. 6(c).
FIG. 5(a) illustrates an IC package obtained by installing, in a package 21 by way of wires 3 and 4, (i) an IC chip 10 including a circuit block 1 and (ii) an IC chip 20 including a circuit block 2, respectively. FIG. 5(b) illustrates an IC package obtained by installing the IC chip 10 in a package 22 by way of the wires 3. FIG. 5(c) illustrates an IC package obtained by installing the IC chip 20 in a package 23 by way of the wires 4. Provided on the IC chips 10 and 20 are circuits 1 and 2, respectively. Note that, in the following explanation, the circuits 1 and 2 are referred to as “circuit blocks 1 and 2”, respectively.
Now, see the conventional method of designing, based on the IC package (see FIG. 5(a)) including the circuit blocks 1 and 2, an IC package merely using either the circuit block 1 or the circuit block 2. In this case, the designing is carried out as follows for the sake of cost reduction. That is, firstly carried out is designing of either (i) the new package 22 having a size and a terminal (pin) layout which are appropriate for the IC chip 10 only including the circuit block 1; or (ii) the new package 23 having a size and a terminal (pin) layout which are appropriate for the IC chip 20 only including the circuit block 2. Then, the package 22 or 23 is manufactured in accordance with the design. Thereafter, the IC chip 10 or 20 each used for the manufacturing of the IC package shown in FIG. 5(a) is installed in the package 22 or 23 thus manufactured, respectively. This makes it possible to manufacture either (i) the IC package (see FIG. 5(b)) including the circuit block 1 or (ii) the IC package (see FIG. 5(c)) including the circuit block 2.
Meanwhile, FIG. 6(a) illustrates an IC package obtained by installing, in a package 51 by way of the wires 3 and 4, an IC chip 8 on which the circuit blocks 1 and 2 are provided. FIG. 6(b) illustrates an IC package obtained by installing the IC chip 10 in the package 22 by way of the wires 3. FIG. 6(c) illustrates an IC package obtained by installing the IC chip 20 in the package 23 by way of the wires 4.
Now, see the conventional method of designing, based on the IC package (see FIG. 6(a)) including the IC chip 8 on which the circuit blocks 1 and 2 are provided, an IC package merely using either the circuit block 1 or the circuit block 2. In this case, the designing is carried out as follows for the sake of cost reduction. That is, firstly carried out is designing of either (i) the IC chip 10 only including the circuit block 1, or (ii) the IC chip 20 only including the circuit block 2. Designed next is either (i) the new package 22 having a size and a terminal (pin) layout which are appropriate for the IC chip 10 thus designed; or (ii) the new package 23 having a size and a terminal (pin) layout which are appropriate for the IC chip 20 thus designed. Then, either (i) the IC chip 10 and the package 22 or (ii) the IC chip 20 and the package 23 are manufactured (prepared) in accordance with the design. Thereafter, the IC chip 10 or 20 is installed in the package 22 or 23 thus manufactured, respectively. This makes it possible to manufacture either (i) the IC package (see FIG. 6(b)) including the circuit block 1 or (ii) the IC package (see FIG. 6(c)) including the circuit block 2.
In the conventional designing method, the package 21 of the IC package (original IC package) used as a base (hereinafter, also referred to as “design base”) of the designing has a size different from the size of the package 22 or 23 of the designed IC package.
So, compare (i) the size of a region 15 of the package 21 (see FIG. 5(a)) of the original IC package, with (ii) a region 25 of the package 22 (see FIG. 5(b)) of the designed IC package. Also, compare (i) the size of a region 15′ of the package 51 (see FIG. 6(a)) of the original IC package, with (ii) the region 25 of the package 22 (see FIG. 6(b)) of the designed IC package. Each of the regions 15 and 15′ is associated with the circuit block 1, and has a width (lengthwise direction in the figures) different from that of the region 25 of the package 22.
In the meanwhile, described in, e.g., Non-patent document 1 are a wireless LAN use dual-band power amplifier “AWL9924” and a wireless LAN use single-band power amplifier “RFS-P2023”, each of which is presumably designed in accordance with a method similar to the aforementioned conventional designing method. The dual-band power amplifier “AWL9924” is a power amplifier used in a so-called “dual-band wireless LAN system”, so that the dual-band power amplifier “AWL9924” is accommodated to (i) wireless LAN (IEEE.802.11b/g) using the 2.4 GHz band and (ii) wireless LAN (IEEE.802.11a) using the 5 GHz band. As described in Non-patent document 1, the dual-band power amplifier “AWL9924” is an IC package including (i) a power amplifier for use in the wireless LAN using the 2.4 GHz band; (ii) a power amplifier for use in the wireless LAN using the 5 GHz band; and (iii) a detector. On the other hand, the single-band power amplifier “RFS-P2023” is a power amplifier used in a so-called “single-band wireless LAN system”, so that the single-band power amplifier “RFS-P2023” is accommodated only to the wireless LAN (IEEE.802.11b/g) using the 2.4 GHz band. As described in Non-patent document 1, the single-band power amplifier “RFS-P2023” is an IC package including (i) a power amplifier for use in the wireless LAN using the 2.4 GHz band; and (ii) a detector. Therefore, in this example, the power amplifier used for the 2.4 GHz wireless LAN corresponds to the circuit block 1; the power amplifier used for the 5 GHz wireless LAN corresponds to the circuit block 2; the dual-band power amplifier “AWL9924” corresponds to the IC package including the circuit blocks 1 and 2; and the single-band amplifier “RFS-P2023” corresponds to the IC package including only the circuit block 1. In this example, the dual-band power amplifier “AWL9924” has a package size of 4 mm×4 mm×1 mm, and the single-band power amplifier “RFS-P2023” has a package size of 3 mm×3 mm×1 mm. Therefore, the dual-band power amplifier “AWL9924” has a package size different from that of the single-band amplifier “RFS-P2023”.
Further, in the conventional designing method, the region 15 (or 15′) of the package 21 (or 51) of the original IC package is generally different from the region 25 of the package 22 of the designed IC package, in terms of the terminal layout. Specifically, the region 15 (or 15′) associated with the circuit block 1 is different from the region 25 associated with the circuit block 1, in terms of the respective positions of terminals 1-1 through 1-6 each connected to the circuit block 1. Similarly, a region 16 (or 16′) of the package 21 (or 51) of the original IC package is generally different from a region 26 of the package 23 of the designed IC package, in terms of the terminal layout. Specifically, the region 16 associated with the circuit block 2 is different from the region 26 associated with the circuit block 2, in terms of the respective positions of terminals 2-1 through 2-6. Note that the wording “region associated with the circuit block 1” refers to a region in which the terminals 1-1 through 1-6 each connected to the circuit block 1, and terminals provided among the terminals 1-1 through 1-6 are positioned. Whereas, the wording “region associated with the circuit block 2” refers to a region in which terminals 2-1 through 2-6 connected to the circuit block 2, and terminals provided among the terminals 2-1 through 2-6 are positioned.
In the meanwhile, described in, e.g., Non-patent documents 2, 3, 4, and 5 are: a dual-band power amplifier “AP2010”, 2.4 GHz single-band power amplifiers “AP1091” and “AP1093”, and a 5 GHz single-band power amplifier “AP2085”, each of which is presumably designed in accordance with a method similar to the aforementioned conventional designing method. In this example, the dual-band power amplifier “AP2010” corresponds to the IC package including the circuit blocks 1 and 2; each of the 2.4 GHz single-band power amplifiers “AP1091” and “AP1093” corresponds to the IC package including only the circuit block 1; and the 5 GHz single-band power amplifier “AP2085” corresponds to the IC package including the circuit block 2. In this example, the 2.4 GHz single-band power amplifiers “AP1091” and “AP1093”, and the 5 GHz single-band power amplifier “AP2085” are different from the dual-band power amplifier “AP2010” in terms of the terminal layout, as described in Non-patent documents 2, 3, 4, and 5.
In the example shown in FIG. 5(a) through FIG. 5(c), compare (i) the terminal layout of the region 15 of the package 21 (see FIG. 5(a)) of the original IC package, with (ii) the terminal layout of the region 25 of the package 22 (see FIG. 5(b)) of the designed IC package. Also, in the example shown in FIG. 6(a) through FIG. 6(c), compare (i) the terminal layout of the region 15′ of the package 51 (see FIG. 6(a)) of the original IC package, with (ii) the terminal layout of the region 25 of the package 22 (see FIG. 6(b)) of the designed IC package. Each of the comparisons clarifies that the terminal layouts are different from each other. Each of the regions 15, 15′, and 25 is associated with the circuit block 1.
The present applicants have invented unprecedented and new designing method and manufacturing method, recently. The methods are now publicly known. In the methods, an IC package using a plurality of circuit blocks is used as a base in designing an IC package using a part of the circuit blocks; however, the IC package thus designed has the same terminal layout and size as those of the original IC package. The following explains an example of such new designing method and manufacturing method, with reference to FIG. 7(a), FIG. 7(b), FIG. 8(a), and FIG. 8(b). For ease of explanation, materials having the equivalent functions as those shown in either FIG. 5(a) through FIG. 5(c) or FIG. 6(a) through FIG. 6(c) will be given the same reference symbols, and explanation thereof will be omitted here.
FIG. 7(a) illustrates an IC package 11 obtained by installing, in a package 11a by way of the wires 3 and 4, (i) the IC chip 10 on which the circuit block 1 is provided and (ii) the IC chip 20 on which the circuit block 2 is provided. FIG. 7(b) illustrates an IC package 31 obtained by installing the IC chip 10 in the IC package 11 by way of the wires 3.
In the designing method, when the new IC package 31 using only the IC chip 10 is designed based on the IC package 11 including the IC chips 10 and 20, the IC chip 20 not to be used is simply omitted. Accordingly, a method for manufacturing such an IC package 31 is the same as a method for manufacturing the IC package 11 shown in FIG. 7(a), except that the method for manufacturing the IC package 31 does not includes a step of installing the IC chip 20 in the package 11a. In accordance with such a manufacturing method, the IC package 31 shown in FIG. 7(b) is manufactured.
FIG. 8(a) illustrates an IC package 17 obtained by installing, in the package 11a by way of the wires 3 and 4, an IC chip 7 on which the circuit blocks 1 and 2 are provided. FIG. 8(b) illustrates an IC package 41 obtained by installing the IC chip 7 in the package 11a by way of the wires 4.
In the designing method, when the new IC package 41 using only the circuit block 2 is designed based on the IC package 17 (see FIG. 8(a)) using the circuit blocks 1 and 2, the wires 3 associated with the circuit block 1 not to be used is omitted. Accordingly, a method for manufacturing such an IC package 41 is the same as a method for manufacturing the IC package 17 shown in FIG. 8(a), except that the method for manufacturing the IC package 41 does not includes a step of carrying out wiring with respect to the circuit block 1 not to be used, i.e., does not include a step of connecting the IC chip 7 to terminals of the package 11a by way of the wires 3. In accordance with such a manufacturing method, the IC package 41 shown in FIG. 8(b) is manufactured.
The package 11a of the IC package 31 designed and manufactured in accordance with the above methods has a region 5 whose structure is the same as that of a region 5 of the package 11a of the original IC package 11. Similarly, the package 11a of the IC package 41 designed and manufactured in accordance with the above methods has a region 6′ whose structure is the same as that of a region 6′ of the original IC package 17. Each of the regions 5 is associated with the circuit block 1, and each of the regions 6′ is associated with the circuit block 2. As such, the IC packages 31 and 41 designed and manufactured in accordance with the above methods have the same terminal layouts as those of the original IC packages, respectively. See the following specific example. That is, a single-band power amplifier provided by SHARP CORPORATION and described in p. 152 of Non-patent document 6 is designed based on a dual-band power amplifier provided by SHARP CORPORATION and described in p. 152 of Non-patent document 6, although this fact is not described therein. For this reason, the single-band power amplifier and the dual-band power amplifier have a common terminal layout.
Note that each of FIG. 5(a) through FIG. 5(c) and FIG. 6(a) through FIG. 6(c) illustrates one example of the IC package designed by the present inventors in accordance with each of the publicly know techniques, so that each of the figures does not illustrate the publicly known technique itself.
Non-patent document 1: ANADIGICS, Inc., “WLAN PAs” (brochure), [online], published on July 2004, [Accessed on Dec. 31, 2000], Internet <URL: http://www.anadigics.com/products/addrefs/Brochure/WL AN_Brochure_(07-2004)_web.pdf>
Non-Patent document 2: RF Integrated Corp., “AP2010 2.4 & 5 GHz Dual Band Power Amplifier Data Sheet”, [online], published on Dec. 15, 2004 [Accessed on Jan. 12, 2005], Internet <URL: http://www.rfintc.com/pdf_file/AP2010.pdf>
Non-patent document 3: RF Integrated Corp., “AP1091 2.4 GHz Power Amplifier Data Sheet”, [online], published on Mar. 27, 2003, [Accessed on Jan. 12, 2005], Internet <URL: http://www.rfintc.com/pdf_file/AP1091.pdf>
Non-patent document 4: RF Integrated Corp., “AP1093 2.4 GHz Power Amplifier Data Sheet”, [online], published on Aug. 6, 2004, [Accessed on Jan. 12, 2005], Internet <URL: http://www.rfintc.com/pdf_file/AP1093.pdf>
Non-Patent document 5: RF Integrated Corp., “AP2085 5 GHz Power Amplifier Data Sheet”, [online], published on Aug. 30, 2004 [Accessed on Jan. 12, 2005], Internet <URL: http://www.rfintc.com/pdf_file/AP2085.pdf>
Non-Patent document 6: “Basis of Wireless Data Communication and Utilization of RF Components” edited by Transistor Technique Editorial Department, CQ publishing. Co. Ltd., published on Dec. 1, 2003, p.p. 152-166.
In each of the conventional techniques explained with reference to FIG. 5(a) through FIG. 5(c) and FIG. 6(a) through FIG. 6(c), the package and the terminal layout of the IC package to be designed, i.e., the package and the terminal layout of the IC package merely using either the circuit block 1 or the circuit block 2 are determined in accordance with (i) the size of the IC chip (10 or 20) to be used, (ii) the number of the terminals, and (iii) the easiness in the wire layout. Accordingly, the package and the terminal layout of the designed IC package are changed from the package and the terminal layout of the original IC package, i.e., the IC package using the circuit blocks 1 and 2. Such a change in the package and the terminal layout generally causes a change of a property of the IC package. For example, see a case where each of the IC packages is a circuit for processing a high-frequency signal, such as a high-frequency wireless communication amplifier. In this case, the change in the layout of terminals (input terminal and output terminal) for transmitting the high-frequency signal causes a change of a property (e.g., amplification property) of the IC package. This possibly causes no problem in some cases, i.e., depending on a function of the circuit block to be used; however, in many cases, this requires changes of a pattern and peripheral elements each provided in a substrate in which the IC package using the circuit blocks 1 and 2 is installed. Specifically, the pattern and the peripheral elements in the substrate need to be changed so as to be accommodated to the IC package using either the circuit block 1 or the circuit block 2. For example, in cases where each of the circuit blocks 1 and 2 is an IC for processing a microwave-band high-frequency signal, the pattern and the peripheral circuit elements each provided in the substrate need to be changed so as to be accommodated to the IC package using either the circuit block 1 or the circuit block 2. Moreover, the pattern provided in the substrate in which the IC package using either the circuit block 1 or the circuit block 2 is installed serves as a part of the circuit in the case where each of the circuit blocks 1 and 2 is the IC for processing the microwave-band high-frequency signal, so that the change of the pattern provided in the substrate is not only a physical change of the wire pattern, but also a change of the circuit structure. This possibly requires a further adjustment.
This is specifically explained, e.g., as follows. In FIG. 5(a) through FIG. 5(c) and FIG. 6(a) through FIG. 6(c), assume that: the circuit block 1 is a 2.5 GHz band wireless LAN power amplifier for amplifying a high-frequency signal used in the 2.5 GHz band wireless LAN, and the circuit block 2 is a 5 GHz band wireless LAN power amplifier for amplifying a high-frequency signal used in the 5 GHz band wireless LAN. A glass epoxy substrate is used as the substrate on which the IC package is provided. Such a glass epoxy substrate is an insulative plate manufactured by impregnating a fiberglass fabric with an epoxy resin, and is frequently used in general as the substrate on which the IC package is provided. In such a substrate, the high-frequency signal used in the 2.5 GHz wireless LAN has an equivalent wavelength of approximately 6 cm, whereas the high-frequency signal used in the 5 GHz wireless LAN has an equivalent wavelength of approximately 3 cm. Each of the high-frequency signals having such equivalent wavelengths has such a phase that is considerably deviated by deviation of the wire. For example, when the wire is deviated by 4 mm so as to connect (i) the circuit block for processing the high-frequency signal used in the 5 GHz band wireless LAN to (ii) a peripheral component, the phase of the high-frequency signal is deviated by 45°. This causes respective changes of (i) the property of the IC package, and (ii) the property of the substrate in which the IC package is installed. Similarly, when an IC pattern of the IC chip is changed, the phase of the high frequency signal is deviated, with the result that the property of the IC package is changed. Further, the change of the IC pattern of such an IC chip for processing the high-frequency signal requires a great risk because the IC pattern needs to be determined in consideration of cross talk and radiation power each pertaining to such a high-frequency signal. For this reason, it is preferable that the IC pattern never be changed as much as possible once the IC pattern is determined in consideration of the cross talk and the radiation power each pertaining to such a high-frequency signal.
Such a problem is solved by the designing method explained with reference to FIG. 7(a), FIG. 7(b), FIG. 8(a) and FIG. 8(b) because the designing method requires no redesigning of the IC pattern.
However, the IC package designed in accordance with the designing method explained with reference to FIG. 7(a), FIG. 7(b), FIG. 8(a) and FIG. 8(b) merely needs the half of the circuit blocks, but requires a package area as large as that of the original IC package. For this reason, the designing method explained with reference to FIG. 7(a), FIG. 7(b), FIG. 8(a) and FIG. 8(b) is not suitable for designing of a small-size IC package. Moreover, each of the IC packages designed in accordance with the designing method has a package size larger than that of each of the IC package designed in accordance with the designing method explained with reference to FIG. 5(a) through FIG. 5(c), FIG. 6(a) through FIG. 6(c). This causes cost increase of the IC.